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| RF5110 0 Typical Applications * 3V GSM Cellular Handsets * 3V Dual-Band/Triple-Band Handsets * GPRS Compatible Product Description -A3.00 SQ. 3V GSM POWER AMPLIFIER * Commercial and Consumer Systems * Portable Battery-Powered Equipment 0.15 C A 2 PLCS The RF5110 is a high-power, high-efficiency power amplifier module offering high performance in GSM OR GPRS applications. The device is manufactured on an advanced GaAs HBT process, and has been designed for use as the final RF amplifier in GSM hand-held digital cellular equipment and other applications in the 800MHz to 950MHz band. On-board power control provides over 70dB of control range with an analog voltage input, and provides power down with a logic "low" for standby operation. The device is self-contained with 50 input and the output can be easily matched to obtain optimum power and efficiency characteristics. The RF5110 can be used together with the RF5111 for dual-band operation. The device is packaged in an ultra-small 3mmx3mmx1mm plastic package, minimizing the required board space. Optimum Technology Matching(R) Applied Si BJT Si Bi-CMOS InGaP/HBT GaAs HBT SiGe HBT GaN HEMT GaAs MESFET Si CMOS SiGe Bi-CMOS 1.00 0.85 0.80 0.65 0.05 C 1.50 TYP 2 PLCS 0.15 C B 0.05 0.01 12 MAX 2 PLCS 0.15 C B -B1.37 TYP 2 PLCS 0.15 C A -CDimensions in mm. 0.10 M C A B SEATING PLANE 2.75 SQ. 0.60 0.24 TYP 0.45 0.00 4 PLCS Shaded lead is pin 1. 0.30 0.18 1.65 SQ. 1.35 0.23 0.13 4 PLCS 0.50 0.55 0.30 Package Style: QFN, 16-Pin, 3x3 Features * Single 2.7V to 4.8V Supply Voltage * +36dBm Output Power at 3.5V APC1 APC2 VCC NC * 32dB Gain with Analog Gain Control * 57% Efficiency 12 11 10 9 RF OUT RF OUT RF OUT RF OUT 16 VCC1 GND1 RF IN GND2 1 2 3 4 5 VCC2 15 14 13 * 800MHz to 950MHz Operation * Supports GSM and E-GSM Ordering Information RF5110 RF5110 PCBA 3V GSM Power Amplifier Fully Assembled Evaluation Board 6 VCC2 7 NC 8 2f0 Functional Block Diagram RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com Rev A0 050318 2-1 RF5110 Absolute Maximum Ratings Parameter Supply Voltage Power Control Voltage (VAPC1,2) DC Supply Current Input RF Power Duty Cycle at Max Power Output Load VSWR Operating Case Temperature Storage Temperature Rating -0.5 to +6.0 -0.5 to +3.0 2400 +13 50 10:1 -40 to +85 -55 to +150 Unit VDC V mA dBm % C C Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Parameter Overall Operating Frequency Range Usable Frequency Range Maximum Output Power Total Efficiency Specification Min. Typ. Max. Unit Condition Temp=25C, VCC =3.6V, VAPC1,2 =2.8V, PIN =+4.5dBm, Freq=880MHz to 915MHz, 37.5% Duty Cycle, pulse width=1731s See evaluation board schematic. Using different evaluation board tune. Temp=25C, VCC =3.6V, VAPC1,2 =2.8V Temp=+60C, VCC =3.3V, VAPC1,2 =2.8V At POUT,MAX, VCC =3.6V POUT =+20dBm POUT =+10dBm RBW=100kHz, 925MHz to 935MHz, POUT,MIN 880 to 915 800 to 950 34.5 57 12 5 +7.0 Input Power for Max Output Output Noise Power +4.5 +9.5 -72 MHz MHz dBm dBm % % % dBm dBm -81 dBm Forward Isolation Second Harmonic Third Harmonic All Other Non-Harmonic Spurious Input Impedance Optimum Source Impedance Input VSWR Output Load VSWR Stability Ruggedness Output Load Impedance 8:1 10:1 -20 -25 -22 -7 -7 -36 dBm dBm dBm dBm 50 40+j10 2.5:1 4:1 For best noise performance POUT,MAX-5dB V V dB dB/V pF mA A ns Power Control VAPC1 VAPC2 Power Control "ON" Power Control "OFF" Power Control Range Gain Control Slope APC Input Capacitance APC Input Current Turn On/Off Time 2-2 Rev A0 050318 RF5110 Parameter Power Supply Power Supply Voltage 2.7 3.5 4.8 5.5 2 200 1 1 V V V A mA A A Specifications Nominal operating limits, POUT <+35dBm With maximum output load VSWR 6:1, POUT <+35dBm DC Current at POUT,MAX Idle Current, PIN <-30dBm PIN <-30dBm, VAPC1,2 =0.2V PIN <-30dBm, VAPC1,2 =0.2V, Temp=+85C Specification Min. Typ. Max. Unit Condition Power Supply Current 15 335 10 10 Rev A0 050318 2-3 RF5110 Pin 1 Function VCC1 Description Power supply for the pre-amplifier stage and interstage matching. This pin forms the shunt inductance needed for proper tuning of the interstage match. Refer to the application schematic for proper configuration. Note that position and value of the components are important. Ground connection for the pre-amplifier stage. Keep traces physically short and connect immediately to the ground plane for best performance. It is important for stability that this pin has it's own vias to the groundplane, to minimize any common inductance. RF Input. This is a 50 input, but the actual impedance depends on the interstage matching network connected to pin 1. An external DC blocking capacitor is required if this port is connected to a DC path to ground or a DC voltage. Interface Schematic See pin 3. 2 GND1 See pin 1. 3 RF IN VCC1 RF IN From Bias GND1 Stages 4 GND2 5 VCC2 Ground connection for the driver stage. To minimize the noise power at See pin 3. the output, it is recommended to connect this pin with a trace of about 40mil to the ground plane. This will slightly reduce the small signal gain, and lower the noise power. It is important for stability that this pin have it's own vias to the ground plane, minimizing common inductance. Power supply for the driver stage and interstage matching. This pin forms the shunt inductance needed for proper tuning of the interstage match. Please refer to the application schematic for proper configuration, and note that position and value of the components are important. Same as pin 5. Not connected. Connection for the second harmonic trap. This pin is internally connected to the RF OUT pins. The bonding wire together with an external capacitor form a series resonator that should be tuned to the second harmonic frequency in order to increase efficiency and reduce spurious outputs. RF Output and power supply for the output stage. Bias voltage for the final stage is provided through this wide output pin. An external matching network is required to provide the optimum load impedance. Same as pin 9. VCC2 From Bias GND2 Stages 6 7 8 VCC2 NC 2F0 9 RF OUT RF OUT From Bias Stages GND PCKG BAS 10 11 12 13 14 15 16 RF OUT RF OUT RF OUT NC VCC APC2 APC1 Same as pin 9. Same as pin 9. Same as pin 9. Not connected. Power supply for the bias circuits. Power Control for the output stage. See pin 16 for more details. Power Control for the driver stage and pre-amplifier. When this pin is "low," all circuits are shut off. A "low" is typically 0.5V or less at room temperature. A shunt bypass capacitor is required. During normal operation this pin is the power control. Control range varies from about 1.0V for -10dBm to 2.6V for +35dBm RF output power. The maximum power that can be achieved depends on the actual output matching; see the application information for more details. The maximum current into this pin is 5mA when VAPC1 =2.6V, and 0mA when VAPC =0V. Same as pin 9. Same as pin 9. See pin 16. APC VCC To RF Stages GND GND Pkg Base GND Ground connection for the output stage. This pad should be connected to the ground plane by vias directly under the device. A short path is required to obtain optimum performance, as well as to provide a good thermal path to the PCB for maximum heat dissipation. 2-4 Rev A0 050318 RF5110 Theory of Operation and Application Information The RF5110 is a three-stage device with 32 dB gain at full power. Therefore, the drive required to fully saturate the output is +3dBm. Based upon HBT (Heterojunction Bipolar Transistor) technology, the part requires only a single positive 3V supply to operate to full specification. Power control is provided through a single pin interface, with a separate Power Down control pin. The final stage ground is achieved through the large pad in the middle of the backside of the package. First and second stage grounds are brought out through separate ground pins for isolation from the output. These grounds should be connected directly with vias to the PCB ground plane, and not connected with the output ground to form a so called "local ground plane" on the top layer of the PCB. The output is brought out through the wide output pad, and forms the RF output signal path. The amplifier operates in near Class C bias mode. The final stage is "deep AB", meaning the quiescent current is very low. As the RF drive is increased, the final stage self-biases, causing the bias point to shift up and, at full power, draws about 2000mA. The optimum load for the output stage is approximately 2.6. This is the load at the output collector, and is created by the series inductance formed by the output bond wires, vias, and microstrip, and 2 shunt capacitors external to the part. The optimum load impedance at the RF Output pad is 2.6-j1.5. With this match, a 50 terminal impedance is achieved. The input is internally matched to 50 with just a blocking capacitor needed. This data sheet defines the configuration for GSM operation. The input is DC coupled; thus, a blocking cap must be inserted in series. Also, the first stage bias may be adjusted by a resistive divider with high value resistors on this pin to VPC and ground. For nominal operation, however, no external adjustment is necessary as internal resistors set the bias point optimally. VCC1 and VCC2 provide supply voltage to the first and second stage, as well as provides some frequency selectivity to tune to the operating band. Essentially, the bias is fed to this pin through a short microstrip. A bypass capacitor sets the inductance seen by the part, so placement of the bypass cap can affect the frequency of the gain peak. This supply should be bypassed individually with 100pF capacitors before being combined with VCC for the output stage to prevent feedback and oscillations. The RF OUT pin provides the output power. Bias for the final stage is fed to this output line, and the feed must be capable of supporting the approximately 2A of current required. Care should be taken to keep the losses low in the bias feed and output components. A narrow microstrip line is recommended because DC losses in a bias choke will degrade efficiency and power. While the part is safe under CW operation, maximum power and reliability will be achieved under pulsed conditions. The data shown in this data sheet is based on a 12.5% duty cycle and a 600s pulse, unless specified otherwise. The part will operate over a 3.0V to 5.0V range. Under nominal conditions, the power at 3.5V will be greater than +34.5dBm at +90C. As the voltage is increased, however, the output power will increase. Thus, in a system design, the ALC (Automatic Level Control) Loop will back down the power to the desired level. This must occur during operation, or the device may be damaged from too much power dissipation. At 5.0V, over +38dBm may be produced; however, this level of power is not recommended, and can cause damage to the device. The HBT breakdown voltage is >20V, so there are no issue with overvoltage. However, under worst-case conditions, with the RF drive at full power during transmit, and the output VSWR extremely high, a low load impedance at the collector of the output transistors can cause currents much higher than normal. Due to the bipolar nature of the devices, there is no limitation on the amount of current de device will sink, and the safe current densities could be exceeded. High current conditions are potentially dangerous to any RF device. High currents lead to high channel temperatures and may force early failures. The RF5110 includes temperature compensation circuits in the bias network to stabilize the RF transistors, thus limiting the current through the amplifier and protecting the devices from damage. The same mechanism works to compensate the currents due to ambient temperature variations. To avoid excessively high currents it is important to control the VAPC when operating at supply voltages higher than 4.0V, such that the maximum output power is not exceeded. Rev A0 050318 2-5 RF5110 Internal Schematic VCC1 VCC2 RF OUT 5 4.5 pF APC1 RF IN VCC APC2 VCC 5 1.0 k APC1 400 300 PKG BASE GND2 PKG BASE 2-6 Rev A0 050318 RF5110 Evaluation Board Schematic GSM850 Lumped Element J3 VAPC 50 strip VCC VCC P1 P1-1 P1-2 C18 3.3 F VCC1 C2 10 nF C3 1 nF C19 27 pF L1 11 nH C17 10 nF 16 1 2 3 R1 180 4 5 L2 10 Ferrite VCC2 + C21 3.3 F C5 10 nF C6 1 nF C20 13 pF C7 33 pF L6 1.6 nH 6 7 8 C9 and C10 share the same pad. P2 VCC VCC GND GND P2-1 1 2 3 CON3 VAPC GND GND 1 2 3 4 CON4 VAPC C16 10 nF 15 14 13 C15 33 pF 12 11 10 9 L3 8.8 nH 60 mils C14 33 pF L4 1.8 nH 65 mils 40 mils + C13 1 nF J1 RF IN 50 strip C1 56 pF C12 56 pF C11 9.1 pF 50 strip J2 RF OUT C9 15 pF C10 2 pF C8 1.5 pF Rev A0 050318 2-7 RF5110 Evaluation Board Schematic GSM900 Lumped Element J3 VAPC 50 strip VCC VCC P1 P1-1 P1-2 C18 3.3 F VCC1 C2 10 nF C3 1 nF C19 27 pF L1 11 nH C17 10 nF 16 1 2 3 R1 180 4 5 L2 10 Ferrite VCC2 + C21 3.3 F C5 10 nF C6 1 nF C20 15 pF C23 27 pF C7 27 pF L6 1.6 nH 6 7 8 C9 and C10 share the same pad. P2 VCC VCC GND GND P2-1 1 2 3 CON3 VAPC GND GND 1 2 3 4 CON4 VAPC C16 10 nF 15 14 13 C15 47 pF 12 11 10 9 L3 8.8 nH 55 mils C14 47 pF L4 3.6 nH 39 mils + C13 1 nF J1 RF IN 50 strip C1 56 pF C12 56 pF 50 strip J2 RF OUT C9 15 pF C10 11 pF C11* 5.6 pF *C11 is adjacent to L4. C8 1.5 pF C23 and C27 share the same pad. 2-8 Rev A0 050318 RF5110 Evaluation Board Layout Board Size 2.0" x 2.0" Board Thickness 0.032"; Board Material FR-4; Multi-Layer Rev A0 050318 2-9 RF5110 Typical Test Setup Power Supply V- V+ S+ S- RF Generator Spectrum Analyzer 3dB 10dB/5W Buffer x1 OpAmp Pulse Generator A buffer amplifier is recommended because the current into the VAPC changes with voltage. As an alternative, the voltage may be monitored with an oscilloscope. Notes about testing the RF5110 The test setup shown above includes two attenuators. The 3dB pad at the input is to minimize the effect on the signal generator as a result of switching the input impedance of the PA. When VAPC is switched quickly, the resulting input impedance change can cause the signal generator to vary its output signal, either in output level or in frequency. Instead of an attenuator an isolator may also be used. The attenuator at the output is to prevent damage to the spectrum analyzer, and should be sized accordingly to handle the power. It is important not to exceed the rated supply current and output power. When testing the device at higher than nominal supply voltage, the VAPC should be adjusted to avoid the output power exceeding +36dBm. During load-pull testing at the output it is important to monitor the forward power through a directional coupler. The forward power should not exceed +36dBm, and VAPC needs to be adjusted accordingly. This simulates the behavior for the power control loop. To avoid damage, it is recommended to set the power supply to limit the current during the burst not to exceed the maximum current rating. 2-10 Rev A0 050318 RF5110 PCB Design Requirements PCB Surface Finish The PCB surface finish used for RFMD's qualification process is electroless nickel, immersion gold. Typical thickness is 3inch to 8inch gold over 180inch nickel. PCB Land Pattern Recommendation PCB land patterns for PFMD components are based on IPC-7351 standards and RFMD empirical data. The pad pattern shown has been developed and tested for optimized assembly at RFMD. The PCB land pattern has been developed to accommodate lead and package tolerances. Since surface mount processes vary from company to company, careful process development is recommended. PCB Metal Land Pattern A = 0.64 x 0.28 (mm) Typ. B = 0.28 x 0.64 (mm) Typ. C = 1.50 (mm) Sq. Dimensions in mm. 1.50 Typ. 0.50 Typ. Pin 16 B Pin 1 B B B Pin 12 A 0.50 Typ. A C A A 0.55 Typ. B B B B A A A A 0.75 Typ. 1.50 Typ. Pin 8 0.55 Typ. 0.75 Typ. Figure 1. PCB Metal Land Pattern (Top View) Rev A0 050318 2-11 RF5110 PCB Solder Mask Pattern Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be provided in the master data or requested from the PCB fabrication supplier. A = 0.74 x 0.38 (mm) Typ. B = 0.38 x 0.74 (mm) Typ. C = 1.60 (mm) Sq. Dimensions in mm. 1.50 Typ. 0.50 Typ. Pin 16 B Pin 1 B B B Pin 12 A 0.50 Typ. A C A A 0.55 Typ. B 0.55 Typ. 0.75 Typ. B B B A A A A 0.75 Typ. 1.50 Typ. Pin 8 Figure 2. PCB Solder Mask Pattern (Top View) Thermal Pad and Via Design The PCB land pattern has been designed with a thermal pad that matches the die paddle size on the bottom of the device. Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results. 2-12 Rev A0 050318 |
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